The present invention relates to a semiconductor memory device architecture technology; and, more particularly, to a boosted voltage level detector for a boosted voltage generator.
Generally, most semiconductor memory devices include an internal voltage generator for generating an internal voltage by using a power supply voltage VDD supplied from an external circuit of a chip so that a voltage to be required in the operation of an internal circuit is generated in the memory device itself. The key issue in the architecture of the internal voltage generator is to stably supply the internal voltage in a desired voltage level.
As the scaling down in the line width of integrated circuits in the semiconductor memory device is continuously achieved, a low voltage operation based on the power supply voltage is much more general. Accordingly, the architecture technology is also required to satisfy the performance of the device in a low voltage operation.
In this low voltage environment, the semiconductor memory devices have a voltage booster to generate a boosted voltage VPP which is higher than the power supply voltage VDD in order to compensate for the loss of the voltage in the circuits using the power supply voltage VDD and to normally maintain the data processed in the circuits.
Particularly, in DRAM, the boosted voltage VPP has been widely used for the purpose of compensating for the voltage loss caused by a threshold voltage of a MOS transistor in a word line driving circuit, a bit line dividing circuit, a data output buffer, and so on.
Typically, a boosted voltage generator includes a boosted voltage level detector for detecting a voltage level of a boosted voltage VPP based on a reference voltage corresponding to a target voltage, an oscillator for producing a period signal in response to a level detection signal output from the boosted voltage level detector, and a charge pumping circuit for performing an electric charge pumping operation in response to the period signal and for producing the boosted voltage VPP.
FIG. 1 is a circuit diagram of a boosted voltage level detector according to a conventional memory device. The boosted voltage level detector according to the conventional memory device has a voltage divider 100 for dividing the boosted voltage VPP and outputting a divided voltage VPP_REF and a comparison unit 200 which compares the divided voltage VPP_REF with a reference voltage VREFC corresponding to a target voltage and outputting a level detection signal PPE.
The voltage divider 100 has first and second resistors Ra and Rb which are in series connected to each other between a boosted voltage terminal and a ground voltage terminal. The divided voltage VPP_REF, which is an output signal of the voltage divider 100, is a voltage which is determined by a ratio of the resistance values of the first and second resistors Ra and Rb. The divided voltage VPP_REF is output via a common node between the first resistor Ra and the second resistor Rb.
The comparison unit 200 includes a bias NMOS transistor MN11, PMOS transistors MP11 and MP12, NMOS transistors MN12 and MN13 and an inverter INV0. The bias NMOS transistor MN11 is connected to a ground voltage VSS and receives an internal voltage generating enable signal Vgen_ctrl through a gate input terminal thereof. The PMOS transistors MP11 and MP12 are connected to an external power voltage VDD and gates of the PMOS transistors MP11 and MP12 are coupled to each other in order to form a current mirror. The input NMOS transistors MN12 and MN13 are connected to the bias NMOS transistor MN11 and also respectively connected to the PMOS transistors MP11 and MP12. The divided voltage VPP_REF and the reference voltage VREFC, as differential inputs, are applied to two gates of the NMOS transistors MN12 and MN13. The inverter INV0 is connected to a comparison output terminal (common drain of the PMOS transistors MP12 and NMOS transistors MN13) and produces a level detection signal PPE.
The boosted voltage level detector, as described above, detects a state in which the boosted voltage level is lower than a target voltage level, by comparing the divided voltage VPP_REF corresponding to the present boosted voltage VPP with the reference voltage VREFC corresponding to the target boost voltage VPP, by producing the level detection signal PPE in a high level when the divided voltage VPP_REF is higher than the reference voltage VREFC and by producing the level detecting signal PPE in a low level when the divided voltage VPP_REF is lower than the reference voltage VREFC.
However, with the increase of temperature, the conventional level detector of the boosted voltage VPP inevitably undergoes an increasing value of the resistance of the resistors Ra an Rb which are used for producing the divided voltage VPP_REF. That is, the resistors Ra and Rb altogether have a positive temperature coefficient.
Since the resistors Ra and Rb both have the same temperature characteristic, it is difficult to compensate for the loss caused by the resistance variation according to the temperature change. Typically, the reference voltage VREFC has a low electric potential in a low temperature condition. As the level detection signal PPE is based on the level of VREFC, the electrical potential of the boosted voltage VPP is set up less than the target level in a low temperature environment. The boosted voltage level can decrease to a level that generates a test failure. In addition, a write recovery time (tWR) characteristic at the low temperature environment is poor.